block diagram 1 features dual 1.5a totem pole outputs 40nsec rise and fall into 1000pf parallel or push-pull operation single-ended to push-pull conversion high-speed power mosfet compatible low cross-conduction current spike analog latched shutdown internal deadband inhibit circuit low quiescent current 5v to 40v operation thermal shutdown protection cs3706 dual output driver cs3706 description package options 16 lead pdip (internally fused leads) 1 inhibit b 2 3 4 5 6 7 8 inv noninv gnd gnd v out a f/f enable v cc 16 15 14 13 12 11 10 9 inhibit a inhibit ref v in gnd gnd v out b stop + stop - note: all four ground pins must be connected to common ground. december, 2001 - rev. 2 on semiconductor 2000 south county trail, east greenwich, ri 02818 tel: (401)885?600 fax: (401)885?786 n. american technical support: 800-282-9855 web site: www.cherry?emi.com archive device not recommended for new design the cs3706 integrated circuit pro- vides an interface between low- level ttl inputs and high-power switching devices such as power mosfets. a typical application is single-ended pwm control to push- pull power control conversion. the primary function of this device is to convert a bipolar single-ended low current digital input to a pair of totem pole outputs which can source or sink up to 1.5a. an inter- nal flip-flop, driven by double- pulse suppression logic, can be enabled to provide single-ended to push-pull conversion. with the flip- flop disabled, the outputs work in parallel for 3.0a capability. protection functions are also includ- ed for pulse-by-pulse current limit- ing, automatic deadband control and thermal shutdown. f/f enable inhibit a inv v in stop - inhibit ref v out b gnd v out a v cc inhibit b noninv stop + a output logic b output logic - + + - a inh amp b inh amp stop amp digital input logic logic voltage regulator thermal shutdown analog stop latch toggle flip flop +5v q tq +5v +5v +5v +5v +5v +5v +5v +5v r s +v in 130mv block diagram
2 electrical characteristics: these specifications apply over the operating temperature range of the ic. (v in = v cc = 20v, pins 4, 5, 12 &13 = 0v; unless otherwise stated.) parameter test conditions min typ max unit absolute maximum ratings cs3706 logic supply voltage (v in ) .............................................................................................................................. .....................40.0v output supply voltage (v cc ) .............................................................................................................................. .................40.0v output current (each output, source, or sink) steady state ................................................................................................................... ............................................ 500ma peak transient for less than 100 s ............................................................................................. .............................. 1.5a capacitive discharge energy .................................................................................................... ..................................20.0 j digital inputs (inv, noninv) ................................................................................................... ...........................................5.5v analog inputs (stop +, stop -) ................................................................................................. ...........................................v in inhibit inputs (inhibit a, inhibit b, inhibit ref)............................................................................ ..........................5.5v operating temperature range .................................................................................................... ...................................0 to 70?c storage temperature range...................................................................................................... .................................-65 to 150?c lead temperature soldering wave solder (through hole styles only).....................................................................................10 s ec. max, 260? peak notes: all voltages are with respect to the four ground pins which must be connected together. all currents are positive into, neg- ative out of the specified terminal. v in supply current v in = 40v, v cc = 20v, inv = 0v, unused pins = open. 8 12 ma v cc supply current v in = 20v, v cc = 40v, outputs low 3 5 ma v cc leakage current v in = 0v, v cc = 40v 0.05 0.10 ma digital input low level 0.8 v digital input high level 2.2 v digital input current v i = 0v -0.6 -1.0 ma digital input leakage v i = 5v 0.05 0.10 ma output high sat., v c -v out i out = -50ma 2.0 v output high sat., v c -v out i out = -500ma 2.5 v output low sat., v out i out = 50ma 0.4 v output low sat., v out i out = 500ma 2.5 v inhibit threshold v ref = 0.5v 0.4 0.6 v inhibit threshold v ref = 3.5v 3.3 3.7 v inhibit input current v ref = 0v -10 -20 a analog threshold v cm = 0v to 15 v 100 130 150 mv analog input bias current v i = 0v, v cm = 15v -10 -20 a thermal shutdown turn on 155 ?c thermal shutdown turn off 125 ?c
3 cs3706 typical switching characteristics: (v in = v cc = 20v, t a = 25?c. delays measured 50% in to 50% out.) parameter test conditions output c l = unit from inv. input to output: open 1.0 2.2 nf rise time delay 110 130 140 ns 10% to 90% rise 20 40 60 ns fall time delay 80 90 110 ns 90% to 10% fall 25 30 50 ns from n.i. input to output: rise time delay 120 130 140 ns 10% to 90% rise 20 40 60 ns fall time delay 100 120 130 ns 90% to 10% fall 25 30 50 ns v c cross-conduction output rise 25 ns current spike duration output fall 0 ns inhibit delay inhibit ref. = 1v inhibit = 0.5 to 1.5v 250 ns analog shutdown delay stop (+) ref. = 0 stop (-) input = 0 to 0.5v 180 ns package pin description package pin # pin symbol function 16l pdip (internally fused leads) 1 inhibit b control pin for deadband control on channel b. 2 inv inverting input for output drivers. 3 noninv noninverting input for output drivers. 4 gnd ground. 5 gnd ground. 6v out(a) channel a output. 7 f/f enable controls the phase of the two outputs. f/f enable = gnd out of phase. f/f enable = floating in phase. 8v cc supply voltage (5v to 40v) for output drivers. 9 stop - inverting input for stop latch comparator. 10 stop + noninverting input for stop latch comparator. 11 v out(b) channel b output. 12 gnd ground. 13 gnd ground. 14 v in supply voltage (5v to 40v) for ic (except output driver). 15 inhibit ref reference input for deadband control. 16 inhibit a control pin for deadband control on channel a.
4 outputs the totem-pole outputs have been designed to minimize cross-conduction current spikes while maximizing fast, high-current rise and fall times. current limiting can be done externally either at the outputs or at the common v cc pin. the output diodes included have slow recovery and should be shunted with high-speed external diodes when driving high-frequency inductive loads. flip/flop grounding f/f enable activates the internal flip-flop to alternate the two outputs. with pin open, the two outputs operate simultaneously and can be paralleled for higher current operation. since the flip-flop is triggered by the digital input, an off-time of at least 200nsec. must be pro- vided to allow the flip/flop to change states. note that the circuit logic is configured such that the ?ff?state is defined as the outputs low. digital inputs with both an inverting and non-inverting input available, either active-high or active-low signals may be accepted. these are true ttl compatible inputs?he threshold is approximately 1.2v with no hysteresis; and external pull- up resistors are not required. inhibit circuit although it may have other uses, this circuit is included to eliminate the need for deadband control when driving rel- atively slow bipolar power transistors. a diode from each inhibit input to the opposite power switch collector will keep one output from turning on until the other has turned-off. the threshold is determined by the voltage on inhibit ref which can be set from 0.5 to 3.5 v. when this circuit is not used, ground inhibit ref and leave inhib- it a&b open. analog shutdown this circuit is included to get a latched shutdown as close to the outputs as possible, from a time standpoint. with an internal 130mv threshold, this comparator has a common- mode range from ground to (v in - 3v). when not used, both inputs should be grounded. the time required for this circuit to latch is inversely proportional to the amount of overdrive but reaches a minimum of 180nsec. as with the flip-flop, an input off-time of at least 200nsec is required to reset the latch between pulses. supply voltage with an internal 5v regulator, this circuit is optimized for use with a 7 to 40v supply, however, with some slight response time degradation, it can also be driven from 5v. when v in is low, the entire circuit is disabled and no cur- rent is drawn from v cc . when combined with a cs384x pwm, the driver bias switch can be used to supply v in to the cs3706. v in switching should be fast as undefined operation of the outputs may occur with v in less than 5v. thermal considerations should the chip temperature reach approximately 155?c, a parallel, non-inverting input is activated driving both out- puts to the low state. circuit description inv. n.i. out hh l lhh hl l lll truth table out = inv and n.i. out = inv or n.i. cs3706
5 cs3706 application diagram 5v 3k 2k input gnd f/f enable inhibit a v outb v outa inhibit b v in v cc cs3706 ref noninv inv 14v 10 ? r l 100 f 100 ? .047 f .047 f 100 ? 10k 10k
6 part number description CS3706GNF16 16 lead pdip (internally fused leads) d lead count metric english max min max min 16l pdip 19.69 18.67 .775 .735 (internally fused leads) 16 lead pdip thermal data (internally fused leads) r jc typ 15 ?c/w r ja typ 50 ?c/w package specification package dimensions in mm (inches) package thermal data ordering information cs3706 on semiconductor and the on logo are trademarks of semiconductor components industries, llc (scillc). on semiconductor reserves the right to make changes without further notice to any products herein. for additional infor- mation and the latest available information, please contact your local on semiconductor representative. ?semiconductor components industries, llc, 2000 archive device not recommended for new design plastic dip (n); 300 mil wide 0.39 (.015) min. 2.54 (.100) bsc 1.77 (.070) 1.14 (.045) d some 8 and 16 lead packages may have 1/2 lead at the end of the package. all specs are the same. .203 (.008) .356 (.014) ref: jedec ms-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022)
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